A Comparison of Heuristics for FPGA Placement

Field-Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain configurable logic and interconnect to provide a means for fast prototyping and also for a cost-effective chip design. The innovative development of FPGAs spurred the invention of a new field in which many different hardware algorithms could execute on a single device [16]. Efficient Computer Aided Design (CAD) tools are required to compile hardware descriptions into bit-stream files that are used to configure the target FPGA to implement the desired circuits. Currently, the compile time, which is dominated by placement and routing phases, can easily take hours or even days to complete for current large (over 8-million gate) FPGAs. Within the next few years the logic capacity of FPGAs will tend to increase dramatically (up to 40-million gates) that prohibitively long compile times may adversely affect instant manufacturability of FPGAs and become intolerable to users seeking very high speed compile. This paper presents several constructive and iterative improvement placement based heuristics that significantly reduce the amount of computation time required to achieve high-quality placements, compared with VPR [9], [8]. Cluster Seed, GRASP and Partitioning based approaches prove to be excellent candidates to generate good starting points in negligible amounts of time. The effectiveness of these constructive based methods are tested by implementing several local search based methods. Meta-heuristics in the form of Tabu Search and a hybrid Simulated Annealing with short-term memory are further implemented to explore and exploit the solution space effectively.